面向多数据流处理的时空并行可重构计算阵列结构

李萌; 解超; 牛兵

doi:10.11959/j.issn.2096-109x.AQ26028

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面向多数据流处理的时空并行可重构计算阵列结构

专栏：算力网络安全 | 更新时间：2026-07-15

- 面向多数据流处理的时空并行可重构计算阵列结构
- Spatiotemporally parallel reconfigurable computing array architecture for multi-data stream processing
- 网络与信息安全学报 2026年12卷第3期页码：179-195
- 作者机构：
  
  1.中电长城科技有限公司，北京 100190
  2.山东融汇物产集团有限公司，山东济宁 272000
- 作者简介：
  
  李萌（1980- ），男，清华大学博士生，中电长城科技有限公司高级工程师，主要研究方向为数据科学与先进计算。
  解超（1986- ），男，硕士，中电长城科技有限公司高级工程师，主要研究方向为数据科学与先进计算。
  牛兵（1980− ）男，山东融汇物产集团有限公司工程技术人员，主要研究方向为物联网、天地一体化信息网络、卫星通信、网络安全等新技术的跟踪及其在矿山方面的智能化应用。
- 基金信息：
- DOI：10.11959/j.issn.2096-109x.AQ26028
  中图分类号： TP393
- 收稿：2026-01-30，
  
  修回：2026-04-18，
  
  纸质出版：2026-06-25
- 稿件说明：
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李萌, 解超, 牛兵. 面向多数据流处理的时空并行可重构计算阵列结构[J]. 网络与信息安全学报, 2026, 12(3): 179-195.

Li Meng, Xie Chao, Niu Bing. Spatiotemporally parallel reconfigurable computing array architecture for multi-data stream processing[J]. Chinese Journal of Network and Information Security, 2026, 12(3): 179-195.
李萌, 解超, 牛兵. 面向多数据流处理的时空并行可重构计算阵列结构[J]. 网络与信息安全学报, 2026, 12(3): 179-195. DOI： 10.11959/j.issn.2096-109x.AQ26028.

Li Meng, Xie Chao, Niu Bing. Spatiotemporally parallel reconfigurable computing array architecture for multi-data stream processing[J]. Chinese Journal of Network and Information Security, 2026, 12(3): 179-195. DOI： 10.11959/j.issn.2096-109x.AQ26028.

摘要

面向高性能智算系统中网络流式数据的高效处理需求，提出了一种时空并行可重构计算阵列结构，并将其应用于智能芯片设计。该架构融合多上下文处理单元与存储增强型微处理单元，支持动态上下文切换、近存计算与流水线并行。通过计算与存储的深度耦合突破存储墙，以时分复用方式提升资源利用率，相较于传统方案，其处理单元利用率提升30%以上，时延降低25%以上，能效得到显著提升。文中详细阐述该架构的并行机制，分析传统架构存在的问题、主流技术路径及所提方案的创新点，并将该关键技术应用于可重构智能网卡芯片设计，为智算中心、AI训练与推理等场景的网络传输提供新的国产化方案。

Abstract

To address the efficient processing requirements of network streaming data in high-performance intelligent computing systems

a spatiotemporally parallel reconfigurable computing array architecture was proposed and applied to the design of intelligent chips. In this architecture

multi-context processing units and storage-enhanced micro-processing units were integrated

and dynamic context switching

near-memory computing

and pipeline parallelism were supported. The memory wall was broken through the deep coupling of computation and storage

and the resource utilization was improved by means of time-division multiplexing. Compared with traditional solutions

the utilization rate of processing units was increased by more than 30%

the latency was reduced by more than 25%

and the energy efficiency was significantly enhanced. In this paper

the parallel mechanism of the proposed architecture was elaborated in detail

the problems existing in traditional architectures

the mainstream technical approaches

and the innovations of this scheme were analyzed

and this key technology was further applied to the design of reconfigurable smart NIC chips. A new domestic solution for network transmission in scenarios such as intelligent computing centers and AI training and inference was thereby provided.

关键词

Keywords

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