基于图Transformer的门级硬件木马检测方法

徐宇航; 于洪; 郑锐

doi:10.11959/j.issn.2096-109x.AQ25240

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基于图Transformer的门级硬件木马检测方法

学术论文 | 更新时间：2026-05-11

- 基于图Transformer的门级硬件木马检测方法
- Gate-level hardware trojan detection method based on graph Transformer
- 网络与信息安全学报 2026年12卷第2期页码：118-131
- 作者机构：
  
  信息工程大学，河南郑州 450001
- 作者简介：
  
  [ "徐宇航（2002- ），男，信息工程大学硕士生，主要研究方向为HT防御和内生安全。" ]
  [ "于洪（1988- ），女，博士，信息工程大学副研究员，主要研究方向为网络空间内生安全和拟态防御。" ]
  [ "郑锐（1999- ），男，信息工程大学硕士生，主要研究方向为芯片设计与验证和高速互联结构设计。" ]
- 基金信息：
  
  国家重点研发计划资助项目(2022YFB4500900)
- DOI：10.11959/j.issn.2096-109x.AQ25240
  中图分类号： TP309
- 收稿：2025-11-01，
  
  修回：2026-03-25，
  
  录用：2026-03-25，
  
  纸质出版：2026-04-25
- 稿件说明：
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徐宇航, 于洪, 郑锐. 基于图Transformer的门级硬件木马检测方法[J]. 网络与信息安全学报, 2026, 12(2): 118-131.

Xu Yuhang, Yu Hong, Zheng Rui. Gate-level hardware trojan detection method based on graph Transformer[J]. Chinese Journal of Network and Information Security, 2026, 12(2): 118-131.
徐宇航, 于洪, 郑锐. 基于图Transformer的门级硬件木马检测方法[J]. 网络与信息安全学报, 2026, 12(2): 118-131. DOI： 10.11959/j.issn.2096-109x.AQ25240.

Xu Yuhang, Yu Hong, Zheng Rui. Gate-level hardware trojan detection method based on graph Transformer[J]. Chinese Journal of Network and Information Security, 2026, 12(2): 118-131. DOI： 10.11959/j.issn.2096-109x.AQ25240.

摘要

图神经网络能够有效学习并检测门级网表中恶意植入的硬件木马（HT），但现有方法通常基于同构、同工艺电路进行训练，导致模型泛化能力受限于训练集的工艺与结构特性，难以应对目标电路与训练集差异所引起的图结构分布偏移。为此，提出了基于图Transformer的门级HT检测方法。首先，将门级网表转换为通用图结构，设计多维特征提取模块捕捉节点的本征属性与拓扑信息。其次，采用三层堆叠图Transformer进行特征编码，捕捉节点间全局依赖关系，融合多层次特征以增强表达能力。最后，引入带梯度反转层的双任务分类器，抑制电路异构性带来的域偏移。在Trust-Hub公共库的实验表明：所提方法在新思90 nm通用库SAED上实现了95.2%的召回率，且相较现有主流方法在F1分数上有所提高；在基于TRIT的大规模数据集上实现了87.9%的平均召回率和85.0%的平均F1分数，能够有效提升HT检测模型在跨工艺或异构网表中的鲁棒性。

Abstract

Graph neural networks can effectively learn and detect maliciously implanted hardware trojans (HT) in gate-level netlists. However

existing methods were usually trained on isomorphic and same-process circuits

which resulted in the generalization ability of the models being limited by the process and structural characteristics of the training set

making it difficult to cope with the graph structure distribution shift caused by the differences between the target circuit and the training set. To address this issue

a gate-level HT detection method based on graph transformer was proposed. Firstly

the gate-level netlist was converted into a general graph structure

and a multi-dimensional feature extraction module was designed to capture the intrinsic attributes and topological information of nodes. Secondly

a three-layer stacked graph Transformer was adopted for feature encoding to capture the global dependencies between nodes

and multi-level features were fused to enhance the expression ability. Finally

a dual-task classifier with a gradient reversal layer was introduced to suppress the domain shift caused by circuit heterogeneity. Experiments at the Trust-Hub public library showed that the proposed method achieved a recall rate of 95.2% on the synopsys 90 nm general library SAED

and its F1-score was improved compared with existing mainstream methods. On the large-scale dataset based on TRIT

it achieved an average recall rate of 87.9% and an average F1-score of 85.0%. This method effectively improves the robustness of HT detection models in cross-process or heterogeneous netlists.

关键词

Keywords

references

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