基于分段查找表与动态CG-NTT复用的同态ReLU加速

廖颖龙; 罗羽乔; 李丹婕; 李灵武; 姚磊; 蒋琳; 方俊彬

doi:10.11959/j.issn.2096-109x.AQ25232

您当前的位置：

首页 >

文章列表页 >

基于分段查找表与动态CG-NTT复用的同态ReLU加速

学术论文 | 更新时间：2026-07-15

- 基于分段查找表与动态CG-NTT复用的同态ReLU加速
- Accelerating homomorphic ReLU via segmented lookup table and dynamic CG-NTT reuse
- 网络与信息安全学报 2026年12卷第3期页码：135-153
- 作者机构：
  
  1.暨南大学物理与光电工程学院，广东广州 510632
  2.暨南大学智能科学与工程学院，广东珠海 519070
  3.深圳云安宝科技有限公司，广东深圳 518055
  4.哈尔滨工业大学（深圳）计算机科学与技术学院，广东深圳 518055
  5.教育部“光电混合集成电路”国际合作联合实验室，广东广州 510632
- 作者简介：
  
  廖颖龙（2001- ），男，暨南大学物理与光电工程学院硕士生，主要研究方向为同态加密、硬件加速。
  罗羽乔（2001- ），女，暨南大学智能科学与工程学院硕士生，主要研究方向为人工智能、对抗攻击。
  李丹婕（2000- ），女，暨南大学物理与光电工程学院硕士生，主要研究方向为隐私计算、同态加密。
  李灵武（1999- ），男，暨南大学物理与光电工程学院博士生，主要研究方向为同态加密、硬件加速。
  姚磊（1992- ），男，硕士，深圳云安宝科技有限公司总经理，主要研究方向为隐私计算、数据安全等。
  蒋琳（1980- ），女，博士，哈尔滨工业大学（深圳）教授、博士生导师，主要研究方向为全同态加密、零知识证明、安全多方计算。
  方俊彬（1981- ），男，博士，暨南大学教授、博士生导师，主要研究方向为硬件加速、全同态加密。
- 基金信息：
  
  深圳市科技重大专项(KJZD20240903104301003)
- DOI：10.11959/j.issn.2096-109x.AQ25232
  中图分类号： TP309.2
- 收稿：2025-12-05，
  
  修回：2026-05-03，
  
  纸质出版：2026-06-25
- 稿件说明：
移动端阅览
廖颖龙, 罗羽乔, 李丹婕, 等. 基于分段查找表与动态CG-NTT复用的同态ReLU加速[J]. 网络与信息安全学报, 2026, 12(3): 135-153.

Liao Yinglong, Luo Yuqiao, Li Danjie, et al. Accelerating homomorphic ReLU via segmented lookup table and dynamic CG-NTT reuse[J]. Chinese Journal of Network and Information Security, 2026, 12(3): 135-153.
廖颖龙, 罗羽乔, 李丹婕, 等. 基于分段查找表与动态CG-NTT复用的同态ReLU加速[J]. 网络与信息安全学报, 2026, 12(3): 135-153. DOI： 10.11959/j.issn.2096-109x.AQ25232.

Liao Yinglong, Luo Yuqiao, Li Danjie, et al. Accelerating homomorphic ReLU via segmented lookup table and dynamic CG-NTT reuse[J]. Chinese Journal of Network and Information Security, 2026, 12(3): 135-153. DOI： 10.11959/j.issn.2096-109x.AQ25232.

摘要

全同态加密不支持非线性同态计算，导致隐私保护机器学习中的同态ReLU评估难以直接实现。现有采用高阶多项式近似ReLU激活函数的方案设计大位宽模乘与高阶多项式乘法运算，使得系统吞吐量受限、资源利用率低。对此，提出了一种CPU-FPGA异构协同的同态ReLU评估方案：由CPU端执行ReLU的高阶多项式近似，FPGA端执行同态多项式评估加速。具体而言，首先设计了分段查找表模运算方法，借助双级分解映射机制将大位宽模乘转化为并行高低位查表与线性组合，模乘时延较现有最优方案降低97%。其次，提出动态资源复用CG-NTT架构优化多项式乘法效率，依托固定访存模式实现动态表复用策略，相较于传统NTT架构，减少15%~37%计算单元，降低45%~50.8%运算时延。最后，构建CPU-FPGA异构加速框架，通过相位调优接口与资源协调机制，使同态ReLU评估获得21.4倍加速比。实验验证了该方案在加速密文推理中的可行性，但最耗时的自举操作仍需在CPU端执行。因此，未来研究将聚焦自举操作的硬件加速，以进一步提升密文推理系统的实用性能。

Abstract

Fully homomorphic encryption does not support nonlinear homomorphic computation

making it difficult to directly implement homomorphic ReLU evaluation in privacy-preserving machine learning. Existing schemes that employ high-degree polynomials to approximate the ReLU activation function involve large-bitwidth modular multiplication and high-degree polynomial multiplication operations

resulting in limited system throughput and low resource utilization.To address this

a CPU-FPGA heterogeneous collaborative architecture was proposed for homomorphic ReLU evaluation

with the CPU executing high-degree polynomial approximation and the FPGA accelerating homomorphic polynomial evaluation. Specifically

a segmented lookup table modular reduction algorithm was first designed. By means of a two-level decomposition mapping mechanism

large-bitwidth modular multiplication was converted into parallel high/low-bit lookup table operations and linear combinations. As a result

the modular multiplication delay was reduced by 97% compared to the existing state-of-the-art scheme. Secondly

a dynamic resource-reusing CG-NTT architecture was proposed to optimize polynomial multiplication efficiency. Relying on a fixed memory access pattern

a dynamic table reuse strategy was implemented. Compared with traditional NTT architectures

15%～37% of the computation units were reduced

and 45%～50.8% of the operation latency was decreased. Finally

a CPU-FPGA heterogeneous acceleration framework was constructed. Through a phase-tuning interface and a resource coordination mechanism

a speedup of 21.4 times was achieved for homomorphic ReLU evaluation. The feasibility of the proposed scheme in accelerating ciphertext inference was verified by experiments

although the most time-consuming bootstrapping operation still had to be executed on the CPU side. Therefore

future research will be focused on the hardware acceleration of the bootstrapping operation

in order to further improve the practical performance of the ciphertext inference system.

关键词

Keywords

references

Rivest R L , Adleman L , Dertouzos M L . On data banks and privacy homomorphisms [J ] . Foundations of secure computation , 1978 , 4 ( 11 ): 169 - 180 .

Gentry C . A fully homomorphic encryption scheme [D ] . Stanford : Stanford University , 2009 .

Brakerski Z , Gentry C , Vaikuntanathan V . (Leveled) fully homomorphic encryption without bootstrapping [J ] . ACM Transactions on Computation Theory , 2014 , 6 ( 3 ): 1 - 36 .

Fan J , Vercauteren F . Somewhat practical fully homomorphic encryption [EB ] . 2012 .

Chillotti I , Gama N , Georgieva M , et al . TFHE: fast fully homomorphic encryption over the torus [J ] . Journal of Cryptology , 2020 , 33 ( 1 ): 34 - 91 .

Cheon J H , Kim A , Kim M , et al . Homomorphic encryption for arithmetic of approximate numbers [C ] // Proceedings of the 23rd International Conference on the Theory and Applications of Cryptology and Information Security . Cham : Springer , 2017 : 409 - 437 .

Cheon J H , Han K , Kim A , et al . A full RNS variant of approximate homomorphic encryption [M ] // Selected Areas in Cryptography - SAC 2018 . Cham : Springer , 2019 : 347 - 368 .

Kim T , Kwak H , Lee D , et al . Asymptotically faster multi-key homomorphic encryption from homomorphic gadget decomposition [C ] // Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security . New York : ACM , 2023 : 726 - 740 .

Gilad-Bachrach R , Dowlin N , Laine K , et al . Cryptonets: applying neural networks to encrypted data with high throughput and accuracy [C ] // Proceedings of the 33rd International Conference on International Conference on Machine Learning . JMLR , 2016 : 201 - 210 .

Brutzkus A , Gilad-Bachrach R , Elisha O . Low latency privacy preserving inference [C ] // Proceedings of the 36th International Conference on Machine Learning . PMLR , 2019 : 812 - 821 .

Mishra P , Lehmkuhl R , Srinivasan A , et al . Delphi: a cryptographic inference system for neural networks [C ] // Proceedings of the 2020 Workshop on Privacy-Preserving Machine Learning in Practice . New York : ACM , 2020 : 27 - 30 .

Lou Q , Jiang L . Hemet: a homomorphic-encryption-friendly privacy-preserving mobile neural network architecture [C ] // Proceedings of the 38th International Conference on Machine Learning . PMLR , 2021 : 7102 - 7110 .

Park J , Kim M J , Jung W , et al . AESPA: accuracy preserving low-degree polynomial activation for fast private inference [PP ] . V2. arXiv ( 2022-02-18 )[ 2025-09-05 ] . arXiv: 2201.06699 .

Lee E , Lee J W , No J S , et al . Minimax approximation of sign function by composite polynomial for homomorphic comparison [J ] . IEEE Transactions on Dependable and Secure Computing , 2022 , 19 ( 6 ): 3711 - 3727 .

Huang Y , Gong X S , Kong X Y , et al . EFFACT: a highly efficient full-stack FHE acceleration platform [C ] // Proceedings of the 2025 IEEE International Symposium on High Performance Computer Architecture (HPCA) . Piscataway : IEEE Press , 2025 : 1143 - 1157 .

Cheon S , Lee Y , Kim D , et al . DaCapo: automatic bootstrapping management for efficient fully homomorphic encryption [C ] // Proceedings of the 33rd USENIX Security Symposium (USENIX Security 24). 2024 : 6993 - 7010 .

Ju J H , Park J , Kim J , et al . NeuJeans: private neural network inference with joint optimization of convolution and FHE bootstrapping [C ] // Proceedings of the 2024 ACM SIGSAC Conference on Computer and Communications Security . New York : ACM , 2024 : 4361 - 4375 .

Yang Y H , Xu X C , Zhang H B , et al . Hydra: scale-out FHE accelerator architecture for secure deep learning on FPGA [C ] // Proceedings of the 2025 IEEE International Symposium on High Performance Computer Architecture (HPCA) . Piscataway : IEEE Press , 2025 : 1174 - 1186 .

Zhu Y L , Wang X Y , Ju L , et al . FxHENN: FPGA-based acceleration framework for homomorphic encrypted CNN inference [C ] // Proceedings of the 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA) . Piscataway : IEEE Press , 2023 : 896 - 907 .

Ye T , Kuppannagari S R , Kannan R , et al . Performance modeling and FPGA acceleration of homomorphic encrypted convolution [C ] // Proceedings of the 2021 31st International Conference on Field-Programmable Logic and Applications (FPL) . Piscataway : IEEE Press , 2021 : 115 - 121 .

Han M Q , Zhu Y L , Lou Q , et al . coxHE: a software-hardware co-design framework for FPGA acceleration of homomorphic computation [C ] // Proceedings of the 2022 Design , Automation Test in Europe Conference Exhibition (DATE) . Piscataway : IEEE Press , 2022 : 1353 - 1358 .

Yang Y H , Zhang H Z , Fan S Y , et al . Poseidon: practical homomorphic encryption accelerator [C ] // Proceedings of the 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA) . Piscataway : IEEE Press , 2023 : 870 - 881 .

Mazonka O , Chielle E , Soni D , et al . Fast and compact interleaved modular multiplication based on carry save addition [C ] // Proceedings of the 2022 IEEE/ACM International Conference on Computer Aided Design (ICCAD) . Piscataway : IEEE Press , 2023 : 1 - 9 .

Guan Z Y , Zhu Y Q , Huang Y C , et al . ESC-NTT: an elastic, seamless and compact architecture for multi-parameter NTT acceleration [C ] // Proceedings of the 2024 Design , Automation Test in Europe Conference Exhibition (DATE) . Piscataway : IEEE Press , 2024 : 1 - 6 .

Geng Y , Hu X , Li M H , et al . Rethinking parallel memory access pattern in number theoretic transform design [J ] . IEEE Transactions on Circuits and Systems II: Express Briefs , 2023 , 70 ( 5 ): 1689 - 1693 .

Su Y , Yang B L , Yang C , et al . ReMCA: a reconfigurable multi-core architecture for full RNS variant of BFV homomorphic evaluation [J ] . IEEE Transactions on Circuits and Systems I: Regular Papers , 2022 , 69 ( 7 ): 2857 - 2870 .

Su Y , Yang B L , Yang C , et al . A highly unified reconfigurable multicore architecture to speed up NTT/INTT for homomorphic polynomial multiplication [J ] . IEEE Transactions on Very Large Scale Integration (VLSI) Systems , 2022 , 30 ( 8 ): 993 - 1006 .

Ren X L , Chen Z H , Gu Z , et al . CHAM: a customized homomorphic encryption accelerator for fast matrix-vector product [C ] // Proceedings of the 2023 60th ACM/IEEE Design Automation Conference (DAC) . Piscataway : IEEE Press , 2023 : 1 - 6 .

Chen H , Laine K , Player R . Simple encrypted arithmetic library - SEAL v2.1 [M ] // Financial Cryptography and Data Security . Cham : Springer , 2017 : 3 - 18 .

Öztürk E . Design and implementation of a low-latency modular multiplication algorithm [J ] . IEEE Transactions on Circuits and Systems I: Regular Papers , 2020 , 67 ( 6 ): 1902 - 1911 .

Riazi M S , Laine K , Pelton B , et al . HEAX: an architecture for computing on encrypted data [C ] // Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems . New York : ACM , 2020 : 1295 - 1309 .

Ao W , Boddeti V N . Automated adaption of CNNs for efficient evaluation over FHE [PP ] . V1. arXiv ( 2023-10-12 )[ 2025-09-05 ] . arXiv: 2310.08012 .

Wan J P , Li D J , Fang J B , et al . LPFHE: low-complexity polynomial CNNs for secure inference over FHE [M ] // Computer Security – ESORICS 2024 . Cham : Springer , 2024 : 403 - 423 .

Al Badawi A , Jin C , Lin J , et al . Towards the AlexNet moment for homomorphic encryption: HCNN, the first homomorphic CNN on encrypted data with GPUs [J ] . IEEE Transactions on Emerging Topics in Computing , 2021 , 9 ( 3 ): 1330 - 1343 .

Xu Z H , Ye T , Kannan R , et al . FAST: FPGA acceleration of fully homomorphic encryption with efficient bootstrapping [C ] // Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays . New York : ACM , 2025 : 115 - 126 .

Agrawal R , de Castro L , Yang G W , et al . FAB: an FPGA-based accelerator for bootstrappable fully homomorphic encryption [C ] // Proceedings of the 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA) . Piscataway : IEEE Press , 2023 : 882 - 895 .

Meng X C , Jiang Z J , Lyu Y D . HF-NTT: hazard-free dataflow accelerator for number theoretic transform [PP ] . arXiv ( 2024-10-07 )[ 2025-09-05 ] . arXiv: 2410.04805 .

Im N , Yang H , Eom Y , et al . Efficient twiddle factor generators for NTT [J ] . Electronics , 2024 , 13 ( 16 ): 3128 .

Gribok S , Langhammer M , Pasca B . FPGA modular multipliers using hybrid reduction techniques [C ] // Proceedings of the 2024 34th International Conference on Field-Programmable Logic and Applications (FPL) . Piscataway : IEEE Press , 2024 : 288 - 296 .

顾天晟 , 曾福康 , 邵思思 , 等 . 基于拟态防御和Paillier加密的智能物联网终端安全防护方法 [J ] . 网络与信息安全学报 , 2024 , 10 ( 6 ): 164 - 176 .

Gu T S , Zeng F K , Shao S S , et al . Security protection method based on mimic defense and Paillier encryption for smart IoT terminals [J ] . Chinese Journal of Network and Information Security , 2024 , 10 ( 6 ): 164 - 176 .

王圆圆 , 韩益亮 , 吴立强 , 等 . 智能电网中隐私保护的多维多函数数据聚合方案 [J ] . 网络与信息安全学报 , 2025 , 11 ( 3 ): 163 - 174 .

Wang Y Y , Han Y L , Wu L Q , et al . Privacy-preserving multi-dimensional multi-function data aggregation scheme in smart grid [J ] . Chinese Journal of Network and Information Security , 2025 , 11 ( 3 ): 163 - 174 .

浏览量

下载量

CSCD

文章被引用时，请邮件提醒。

提交

工具集

关联资源

NTRU型无需密钥交换的全同态加密方案

面向异构数据的具有隐私保护性能的公平联邦学习

面向区块链的轻量级抗量子分布式共识方案

面向全服务化网络的安全、隐私、可信及韧性综述

基于谱敏感性识别与稀疏图触发生成器的负荷预测后门攻击方法