基于FPGA的软件定义协议无关解析器

苗力心; 刘勤让; 汪欣

doi:10.11959/j.issn.2096-109x.2020013

您当前的位置：

首页 >

文章列表页 >

基于FPGA的软件定义协议无关解析器

学术论文 | 更新时间：2024-06-03

- 基于FPGA的软件定义协议无关解析器
- Software-defined protocol independent parser based on FPGA
- 网络与信息安全学报 2020年6卷第1期页码：70-76
- 作者机构：
- 作者简介：
  
  [ "苗力心（1995- ），男，辽宁丹东人，国家数字交换系统工程技术研究中心硕士生，主要研究方向为软件定义互连、FPGA" ]
  [ "刘勤让（1975- ），男，河南商丘人，国家数字交换系统工程技术研究中心研究员，主要研究方向为宽带信息网络、片上网络设计" ]
  [ "汪欣（1986- ），男，河南周口人，硕士，主要研究方向为系统结构" ]
- 基金信息：
  
  国家科技重大专项基金资助项目;The National Science Technology Major Program of China(2016X01012101)
- DOI：10.11959/j.issn.2096-109x.2020013
  中图分类号： TP393
- 网络首发：2020-02，
  
  纸质出版：2020-02-15
- 稿件说明：
移动端阅览
苗力心, 刘勤让, 汪欣. 基于FPGA的软件定义协议无关解析器[J]. 网络与信息安全学报, 2020,6(1):70-76.

Lixin MIAO, Qinrang LIU, Xin WANG. Software-defined protocol independent parser based on FPGA[J]. Chinese Journal of Network and Information Security, 2020, 6(1): 70-76.
苗力心, 刘勤让, 汪欣. 基于FPGA的软件定义协议无关解析器[J]. 网络与信息安全学报, 2020,6(1):70-76. DOI： 10.11959/j.issn.2096-109x.2020013.

Lixin MIAO, Qinrang LIU, Xin WANG. Software-defined protocol independent parser based on FPGA[J]. Chinese Journal of Network and Information Security, 2020, 6(1): 70-76. DOI： 10.11959/j.issn.2096-109x.2020013.

摘要

随着信息技术的繁荣发展，各种功能的异构网络层出不穷，异构融合网络成为下一代网络发展的必然趋势。实现异构网络之间的通信，网络转发设备必不可少。传统的转发设备仅支持固定的协议配置，缺乏可扩展性，无法支持新的网络协议。针对这种情况，提出了一种基于FPGA的软件定义协议无关解析器，通过软件定义解析流程，给予解析器灵活可编程的特性，无须对硬件设备进行更改即可完成对多种协议数据包的解析并提取出数据包转发所需的关键信息。通过高性能FPGA平台对解析器进行了实现，并进行了硬件资源开销和性能的评估。实验结果表明，可以完成多种异构网络协议的快速解析，得到完整的解析数据。

Abstract

With the boom of information technology

heterogeneous networks with various functions emerge in endlessly

heterogeneous fusion network has become the inevitable trend of the development of the next generation network.To realize communication between heterogeneous networks

network forwarding equipment is essential.Traditional forwarding devices only support fixed protocol configuration and lack scalability

so they cannot support new network protocols.In view of this situation

a software defined protocol independent parser based on FPGA was proposed.The software defined the parsing process

giving the parser flexible and programmable features.It can analyze multiple protocol packets and extract key information needed for protocol conversion without changing hardware devices.The parser through a high-performance FPGA platform were implemented and hardware resource overhead and performance were evaluated.Experimental results show that it can complete the fast parsing of various heterogeneous network protocols and obtain complete analytical data.

关键词

Keywords

references

FULLER S . RapidIO:the embedded system interconnect [M ] . Piscataway,NJ : WileyPress , 2005

LIU B , ZHANG J D , YANG Q M , et al . Modeling and performance analysis of FC-AE-ASM which base on Petri net theory [C ] // International Conference on Computational Intelligence and Software Engineering . 2011 : 1 - 4 .

NGUYN V G , BRUNSTROM A , GRINNEMO K J , et al . SDN/NFV-based mobile packet core network architectures:a survey [J ] . IEEE Communications Surveys ＆ Tutorials , 2017 , 19 ( 3 ): 1567 - 1602 .

KREUTZ D , RAMOS F M , VERISSIMO P E , et al . Software-defined networking:a comprehensive survey [J ] . Proceedings of the IEEE , 2015 , 103 ( 1 ): 14 - 76 .

PATI S , NARAYANAN R , MEMIK G , et al . Design and implementation of an FPGA architecture for high-speed network feature extraction [C ] // International Conference on Field-Programmable Technology . 2007 : 49 - 56 .

YAZDINEJAD A , BOHLOOLI B , JAMSHIDI K . (2018).Efficient design and hardware implementation of the OpenFlow v1.3 switch on the Virtex-6 FPGA ML605 [J ] . The Journal of Supercomputing , 2017 , 74 ( 3 ): 1299 - 1320 .

LIU T . Implementing Open flow switch using FPGA based platform [J ] .,2014. Department of Telematics , 2014 .

王孝龙 , 刘勤让 , 林森杰 . 一种支持异构协议解析的可配置解析器设计 [J ] . 计算机应用研究 , 2018 , 35 ( 6 ): 1830 - 1833 .

WANG X L , LIU Q R , LIN S J . Configurable parser design for heterogeneous protocols [J ] . Application Research of Computers , 2018 , 35 ( 6 ): 1830 - 1833 .

杨惠 , 冯振乾 , 厉俊男 . 基于FPGA的并行多发可编程解析器 [J ] . 计算机工程与科学 , 2019 , 41 ( 1 ): 24 - 30 .

YANG H , FENG Z Q , LI J N . A multi-concurrent programmable parser based on FPGA [J ] . Computer Engineering ＆ Science , 2019 , 41 ( 1 ): 24 - 30 .

BITAR A , ABDELFATTAH M S , BETZ V . Bringing programmability to the data plane:packet processing with a NoC-enhanced FPGA [C ] // In 2015 International Conference on Field Programmable Technology (FPT) . 2015 : 24 - 31 .

BOSSHART P , DALY D , GIBB G , et al . P4:Programming protocol-independent packet processors [J ] . SIGCOMM Computer Communication Review , 2014 , 44 ( 3 ): 87 - 95

SILVA J S D , BOYER F R , LANGLOIS J M , et al . P4-compatible high-level synthesis of low latency 100 Gbit/s streaming packet parsers in FPGAs [J ] . arXiv preprint arXiv:1711.06613 , 2014 .

BENÁCEK P , PU V , KUBÁTOVÁ H . P4-to-VHDL:automatic generation of 100 Gbit/s packet parsers [C ] // 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) . 2016 : 148 - 155 .

吕平 , 董春雷 , 刘冬培 , 等 . 基于 FPGA 的软件定义流量发生器 [J ] . 通信学报 , 2018 , 39 ( S2 ): 70 - 75 .

LYU P , DONG C L , LIU D P , et al . Implementation of software defined traffic generator based on FPGA [J ] . Journal on Communications , 2018 , 39 ( S2 ): 70 - 75 .

浏览量

595

下载量

CSCD

文章被引用时，请邮件提醒。

提交

工具集

关联资源

基于FPGA的高速国密SM4光纤通信系统方案

基于软件定义的可重构卷积神经网络架构设计

基于软件定义的多协议控制器架构设计

SM3杂凑算法的SoPC组件实现