基于线性脉动阵列的卷积神经网络计算优化与性能分析

刘勤让; 刘崇阳; 周俊; 王孝龙

doi:10.11959/j.issn.2096-109x.2018100

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基于线性脉动阵列的卷积神经网络计算优化与性能分析

学术论文 | 更新时间：2024-06-03

- 基于线性脉动阵列的卷积神经网络计算优化与性能分析
- Based on linear systolic array for convolutional neural network’s calculation optimization and performance analysis
- 网络与信息安全学报 2018年4卷第12期页码：16-24
- 作者机构：
- 作者简介：
  
  [ "刘勤让（1975-），男，河南睢县人，国家数字交换系统工程技术研究中心研究员，主要研究方向为宽带信息网络、片上网络设计。" ]
  [ "刘崇阳（1994-），男，湖北宜昌人，国家数字交换系统工程技术研究中心硕士生，主要研究方向为人工智能、深度学习。" ]
  [ "周俊（1979-），男，湖北黄冈人，国家数字交换系统工程技术研究中心讲师，主要研究方向为芯片设计、宽带信息处理。" ]
  [ "王孝龙（1993-），男，河南民权人，国家数字交换系统工程技术研究中心硕士生，主要研究方向为宽带信息网络、协议解析。" ]
- 基金信息：
  
  国家科技重大专项基金资助项目;The National Science Technology Major Project(2016ZX01012101);国家自然科学基金资助项目;The National Natural Science Foundation of China(61572520);国家自然科学基金创新研究群体基金资助项目;The Foundation for Innovative Research Groups of the National Natural Science Foundation of China(61521003)
- DOI：10.11959/j.issn.2096-109x.2018100
  中图分类号： TP183
- 网络首发：2018-12，
  
  纸质出版：2018-12-15
- 稿件说明：
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刘勤让, 刘崇阳, 周俊, 等. 基于线性脉动阵列的卷积神经网络计算优化与性能分析[J]. 网络与信息安全学报, 2018,4(12):16-24.

Qinrang LIU, Chongyang LIU, Jun ZHOU, et al. Based on linear systolic array for convolutional neural network’s calculation optimization and performance analysis[J]. Chinese Journal of Network and Information Security, 2018, 4(12): 16-24.
刘勤让, 刘崇阳, 周俊, 等. 基于线性脉动阵列的卷积神经网络计算优化与性能分析[J]. 网络与信息安全学报, 2018,4(12):16-24. DOI： 10.11959/j.issn.2096-109x.2018100.

Qinrang LIU, Chongyang LIU, Jun ZHOU, et al. Based on linear systolic array for convolutional neural network’s calculation optimization and performance analysis[J]. Chinese Journal of Network and Information Security, 2018, 4(12): 16-24. DOI： 10.11959/j.issn.2096-109x.2018100.

摘要

针对大部分FPGA端上的卷积神经网络（CNN

convolutional neural network）加速器设计未能有效利用稀疏性的问题，从带宽和能量消耗方面考虑，提出了基于线性脉动阵列的2种改进的CNN计算优化方案。首先，卷积转化为矩阵相乘形式以利用稀疏性；其次，为解决传统的并行矩阵乘法器存在较大I/O需求的问题，采用线性脉动阵列改进设计；最后，对比分析了传统的并行矩阵乘法器和2种改进的线性脉动阵列用于CNN加速的利弊。理论证明及分析表明，与并行矩阵乘法器相比，2种改进的线性脉动阵列都充分利用了稀疏性，具有能量消耗少、I/O带宽占用少的优势。

Abstract

Concerning the issue that the convolutional neural network (CNN) accelerator design on most FPGA ends fails to effectively use the sparsity and considering both bandwidth and energy consumption

two improved CNN calculation optimization strategies based on linear systolic array architecture are proposed.Firstly

convolution is transformed into matrix multiplication to take advantage of sparsity.Secondly

in order to solve the problem of large I/O demand in traditional parallel matrix multiplier

linear systolic array is used to improve the design.Finally

a CNN acceleration comparative analysis of the advantages and disadvantages between parallel matrix multiplier and two improved linear systolic arrays is presented.Theoretical proof and analysis show that compared with the parallel matrix multiplier

the two improved linear systolic arrays make full use of sparsity

and have the advantages of less energy consumption and less I/O bandwidth occupation.

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Keywords

references

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