Spatiotemporally parallel reconfigurable computing array architecture for multi-data stream processing

Li Meng; Xie Chao; Niu Bing

doi:10.11959/j.issn.2096-109x.AQ26028

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Spatiotemporally parallel reconfigurable computing array architecture for multi-data stream processing

Column: Computing Power Network Security | 更新时间：2026-07-15

- Spatiotemporally parallel reconfigurable computing array architecture for multi-data stream processing
- Chinese Journal of Network and Information Security Vol. 12, Issue 3, Pages: 179-195(2026)
- 作者机构：
  
  1.中电长城科技有限公司，北京 100190
  2.山东融汇物产集团有限公司，山东济宁 272000
- 作者简介：
- 基金信息：
- DOI：10.11959/j.issn.2096-109x.AQ26028
  CLC： TP393
- Received：30 January 2026，
  
  Revised：2026-04-18，
  
  Published：25 June 2026
- 稿件说明：
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李萌, 解超, 牛兵. 面向多数据流处理的时空并行可重构计算阵列结构[J]. 网络与信息安全学报, 2026, 12(3): 179-195.

Li Meng, Xie Chao, Niu Bing. Spatiotemporally parallel reconfigurable computing array architecture for multi-data stream processing[J]. Chinese Journal of Network and Information Security, 2026, 12(3): 179-195.
李萌, 解超, 牛兵. 面向多数据流处理的时空并行可重构计算阵列结构[J]. 网络与信息安全学报, 2026, 12(3): 179-195. DOI： 10.11959/j.issn.2096-109x.AQ26028.

Li Meng, Xie Chao, Niu Bing. Spatiotemporally parallel reconfigurable computing array architecture for multi-data stream processing[J]. Chinese Journal of Network and Information Security, 2026, 12(3): 179-195. DOI： 10.11959/j.issn.2096-109x.AQ26028.

摘要

面向高性能智算系统中网络流式数据的高效处理需求，提出了一种时空并行可重构计算阵列结构，并将其应用于智能芯片设计。该架构融合多上下文处理单元与存储增强型微处理单元，支持动态上下文切换、近存计算与流水线并行。通过计算与存储的深度耦合突破存储墙，以时分复用方式提升资源利用率，相较于传统方案，其处理单元利用率提升30%以上，时延降低25%以上，能效得到显著提升。文中详细阐述该架构的并行机制，分析传统架构存在的问题、主流技术路径及所提方案的创新点，并将该关键技术应用于可重构智能网卡芯片设计，为智算中心、AI训练与推理等场景的网络传输提供新的国产化方案。

Abstract

To address the efficient processing requirements of network streaming data in high-performance intelligent computing systems

a spatiotemporally parallel reconfigurable computing array architecture was proposed and applied to the design of intelligent chips. In this architecture

multi-context processing units and storage-enhanced micro-processing units were integrated

and dynamic context switching

near-memory computing

and pipeline parallelism were supported. The memory wall was broken through the deep coupling of computation and storage

and the resource utilization was improved by means of time-division multiplexing. Compared with traditional solutions

the utilization rate of processing units was increased by more than 30%

the latency was reduced by more than 25%

and the energy efficiency was significantly enhanced. In this paper

the parallel mechanism of the proposed architecture was elaborated in detail

the problems existing in traditional architectures

the mainstream technical approaches

and the innovations of this scheme were analyzed

and this key technology was further applied to the design of reconfigurable smart NIC chips. A new domestic solution for network transmission in scenarios such as intelligent computing centers and AI training and inference was thereby provided.

关键词

Keywords

references

曲彤洲 , 戴紫彬 , 陈琳 , 等 . 一种面向序列密码的混合粒度并行运算单元 [J ] . 电子与信息学报 , 2023 , 45 ( 1 ): 78 - 86 .

Qu T Z , Dai Z B , Chen L , et al . A hybrid granularity parallel arithmetical unit for stream cipher [J ] . Journal of Electronics Information Technology , 2023 , 45 ( 1 ): 78 - 86 .

丁博 . 面向异构资源的FPGA动态重构系统自动化设计方法 [D ] . 合肥 : 中国科学技术大学， 2024 .

Ding B . Automated design method for FPGA dynamic reconfiguration system oriented to heterogeneous resources [D ] . Hefei : University of Science and Technology of China , 2024 .

冷静文 , 过敏意 , 曾德泽 , 等 . 数据流芯片的发展现状、趋势与挑战 [J ] . 中国科学: 信息科学 , 2025 , 55 ( 3 ): 452 - 463 .

Leng J W , Guo M Yi , Zeng D Z , et al . Development status, trends and challenges of dataflow chips [J ] . Science China: Information Sciences , 2025 , 58 ( 3 ): 452 - 463 .

张俊也 . 可编程数据中心网络的RDMA传输韧性增强机制 [D ] . 北京 : 北京邮电大学 , 2025 .

Zhang J Y . Resilience enhancement mechanism for RDMA transmission in programmable data center networks [D ] . Beijing : Beijing University of Posts and Telecommunications , 2025 .

Kaiser T , Gottschalk E , Biethahn K , et al . Pasithea-1: an energy-efficient sequential reconfigurable array with CPU-like programmability [J ] . IEEE Open Journal of Circuits and Systems , 2025 , 6 : 1 - 13 .

朱志成 . 基于SIMT架构的智能网卡片外访存优化 [D ] . 武汉 : 华中科技大学 , 2025 .

Zhu Z C . Optimization of off-chip memory access for smart NIC based on SIMT architecture [D ] . Wuhan : Huazhong University of Science and Technology , 2025 .

Han M , Wang L , Xiao L M , et al , ReDas: a lightweight architecture for supporting fine-grained reshaping and multiple dataflows on systolic array [J ] IEEE Transactions on Computers , 2014 , 73 ( 8 ): 1997 - 2011 .

付炫钰 , 李颖颖 . LLM-GEMM：异构计算架构下通用矩阵乘法的自动化代码转换框架 [J ] . 软件导刊， 2026 .

Fu X Y , Li Y Y . LLM-GEMM: an automatic code transformation framework for general matrix multiplication under heterogeneous computing architectures [J ] . Software Guide , 2026 .

中科寒武纪科技股份有限公司 . 思元 590 (MLU590)芯片技术规格说明书 [Z ] . 2025 .

Cambricon Technologies Co., Ltd., Specification manual of MLU 590 (SiYuan 590) Chip [Z ] . 2025.

张多利 , 陈楠 , 汪杨 , 等 . 粗粒度多核系统任务级多线程调度研究 [J ] . 微电子学与计算机 , 2020 , 37 ( 1 ): 46 - 52 .

Zhang D L , Chen N , Wang Y , et al . Research on task-level multi-thread scheduling for coarse-grained multi-core systems [J ] . Microelectronics Computer , 2020 , 37 ( 1 ): 46 - 52 .

Nowatzki T , Gangadhan V , Sankaralingam K , et al . Pushing the limits of accelerator efficiency while retaining programmability [C ] // Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA) . Piscataway : IEEE Press , 2016 : 27 - 39 .

Liu D J , Liu T , Mo X Y , et al . Polyhedral-based pipelining of imperfectly-nested loop for CGRAs [C ] // Proceedings of the 2021 IEEE/ACM International Conference on Computer-Aided Design . Newark, USA : IEEE , 2021 : 1 - 9 .

王彦伟 , 李仁刚 , 徐冉 , 等 . 基于可重构架构的数据中心异构加速软硬件系统级平台 [J ] . 计算机研究与发展 , 2025 , 62 ( 4 ): 963 - 977 .

Wang Y W , Li R G , Xu R , et al . Hardware and software system-level platform for heterogeneous acceleration in data centers based on reconfigurable architecture [J ] . Journal of Computer Research and Development , 2025 , 62 ( 4 ): 963 - 977 .

郭岩松 , 刘雷波 . 一种面向分组密码的粗粒度可重构阵列及AES算法映射 [J ] . 微电子学与计算机， 2015 , 32 ( 9 ): 1 - 5 .

Guo Y S , Liu L B . A block cipher oriented coarse-grained reconfigurable array and AES algorithm mapping [J ] . Microelectronics Computer , 2015 , 32 ( 9 ): 1 - 5 .

Wen T H , Huang J , Huang W , et al . Fusion of memristor and digital compute-in-memory processing for energy-efficient edge computing [J ] . Science , 2024 , 384 ( 6693 ): 325 - 332 .

洪途 , 景乃锋 . 存算解耦合的粗粒度可重构阵列访存结构设计 [J ] . 计算机工程， 2021 , 47 ( 2 ): 239 - 245 .

Hong T , Jing N F . Design of memory access structure for coarse-grained reconfigurable array with decoupled access execute [J ] . Computer Engineering , 2021 , 47 ( 2 ): 239 - 245 .

魏少军 , 李兆石 , 朱建峰 , 等 . 可重构计算：软件可定义的计算引擎 [J ] . 中国科学：信息科学， 2020 , 50 ( 9 ): 1407 - 1426 .

Wei S J , Li Z S , Zhu J F , et al . Reconfigurable computing: toward software defined chips [J ] . Science China Information Sciences , 2020 , 63 ( 9 ): 190401 .

Prabhakar R , Zhang Y Q , Koeplinger D , et al . Plasticine: a reconfigurable architecture for parallel patterns [C ] // Proceedings of the 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA) . Piscataway : IEEE Press , 2017 : 389 - 402 .

窦勇 , 邬贵明 , 徐进辉 , 等 . 支持循环自动流水线的粗粒度可重构阵列体系结构 [J ] . 中国科学(E辑) , 2008 ( 4 ): 579 - 591 .

Dou Y , Wu G M , Xu J H , et al . Coarse-grained reconfigurable array architecture supporting cyclic automatic pipeline [J ] . Science in China (Series E) , 2008 ( 4 ): 579 - 591 .

Hennessy J L , Patterson D A , Kozyrakis C . Computer architecture: a quantitative approach [M ] . 7th ed . Cambridge : Morgan Kaufmann , 2025 .

Chacko V , Anderson J H . Power, performance and area consequences of multi-context support in CGRAs [C ] // Proceedings of the 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors . Newark, USA : IEEE , 2021 : 53 - 58 .

常立博 , 武丹妮 , 杜慧敏 , 等 . 可重构 CNN 处理器的高效能自适应映射策略 [J ] . 计算机辅助设计与图形学学报， 2025 , 37 ( 7 ): 1157 - 1169 .

Chang L B , Wu D N , Du H M , et al . Adaptive mapping for data orchestration in reconfigurable CNN processors via deep reinforcement learning [J ] . Journal of Computer-Aided Design Computer Graphics , 2025 , 37 ( 7 ): 1157 - 1169 .

常立博 , 武丹妮 , 杜慧敏 , 张盛兵 , 郝鹏 , 蔡秀霞 . 可重构 CNN 处理器的高效能自适应映射策略 [J ] . 计算机辅助设计与图形学学报， 2025 , 37 ( 7 ): 1157 - 1169 .

Chang Libo , Wu Danni , Du Huimin , Zhang , et al . Adaptive Mapping for Data Orchestration in Reconfigurable CNN Processors via Deep Reinforcement Learning [J ] . Journal of Computer-Aided Design Computer Graphics , 2025 , 37 ( 7 ): 1157 - 1169 .

张骁 , 周清雷 , 李斌 . 基于HRCA的可重构SM4密码算法研究与实现 [J ] . 网络与信息安全学报 , 2020 , 6 ( 5 ): 101 - 109 .

Zhang X , Zhou Q L , Li B . Research and implementation of reconfigurable SM4 cryptographic algorithm based on HRCA [J ] . Chinese Journal of Network and Information Security , 2020 , 6 ( 5 ): 101 - 109 ..

朱威 , 王友祥 , 杨文聪 , 等 . 面向算网融合的数据处理单元（DPU）技术探索与实践 [J ] . 邮电设计技术， 2025 ( 10 ): 76 - 81 .

Zhu W , Wang Y X , Yang W C , et al . Exploration and practice of data processing Unit (DPU) technology for computing and network convergence [J ] . Posts Telecommunications Design Technology , 2025 ( 10 ): 76 - 81 .

李兆石 . 高灵活可重构处理器的编程模型和硬件架构关键技术研究 [D ] . 北京：清华大学， 2018 .

Li Z S . Research on programming model and key hardware architecture technologies of highly flexible reconfigurable processors [D ] . Beijing : Tsinghua University , 2018 .

张丽果 , 吴凯 , 王文哲 , 等 . 高性能可重构网络协议解析器的设计与实现 [J ] . 西安邮电大学学报 , 2025 , 30 ( 3 ): 58 - 67 ..

Zhang L G , Wu K , Wang W Z , et al . Design and implementation of high-performance reconfigurable network protocol parser [J ] . Journal of Xi’an University of Posts and Telecommunications , 2025 , 30 ( 3 ): 58 - 67 .

浙江大学 . 一种自动支持循环迭代流水线的粗粒度可重构阵列及其配置方法 : 201710712367. X [P ] . 2018-06-19 .

Zhejiang University . A coarse-grained reconfigurable array with automatic support for cyclic iterative pipelines and its configuration method : 201710712367.X [P ] . 2018-06-19 .

曹壮 . 基于可重构的网络报文处理关键技术及快速生成方法研究 [D ] . 长沙 : 国防科技大学 , 2020 .

Cao Z . Research on key technologies and rapid generation method of reconfigurable network packet processing [D ] . Changsha : National University of Defense Technology , 2020 .

张杰 . 面向现代数据中心的智能网卡软硬件协同技术研究 [D ] . 杭州 : 浙江大学 , 2025 .

Zhang J . Research on software-hardware coordination technology of smart NIC for modern data centers [D ] . Hangzhou : Zhejiang University , 2025 .

刘玉 . 可重构网络包处理转发引擎的设计与实现 [D ] . 西安 : 西安电子科技大学 , 2024 .

Liu Y . Design and implementation of reconfigurable network packet processing forwarding engine [D ] . Xi'an : Xidian University , 2024 .

朱博 . 基于可编程网络的多租户虚拟资源管理与优化技术研究 [D ] . 武汉 : 武汉大学 , 2019 .

Zhu B . Research on multi-tenant virtual resource management and optimization technology based on programmable network [D ] . Wuhan : Wuhan University , 2019 .

赵佳欣 , 王竞舟 , 孙玉娥 , 等 . 可重配置数据中心的高效重配置与流量调度算法 [J ] . 计算机研究与发展 , 2026 : 1 - 16 .

Zhao J X , Wang J Z , Sun Y E , et al . Efficient reconfiguration and traffic scheduling algorithm for reconfigurable data centers [J ] . Journal of Computer Research and Development , 2026 : 1 - 16 .

陈杰 , 王俊昌 , 胡嘉晨 , 等 . 面向多样化网络需求的优先级队列流量调度算法 [J ] . 计算机工程 , 2025 , 51 ( 11 ): 152 - 159 .

Chen J , Wang J C , Hu J C , et al . Priority queue traffic scheduling algorithm for diverse network requirements [J ] . Computer Engineering , 2025 , 51 ( 11 ): 152 - 159 .

李宏慧 , 李炜东 , 付学良 . 基于多层虚拟拓扑节能的SDN数据中心网络流量调度算法 [J ] . 计算机应用与软件 , 2021 , 38 ( 4 ): 116 - 122 .

Li H H , Li W D , Fu X L . Energy-efficient traffic scheduling algorithm for SDN data center networks based on multi-layer virtual topology [J ] . Computer Applications and Software , 2021 , 38 ( 4 ): 116 - 122 .

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