LI P J, SHEN J L, GUO W, et al. Secure multidimensional interconnection network for the software defined system on wafer[J]. Chinese Journal of Network and Information Security, 2025, 11(2): 102-114.
LI P J, SHEN J L, GUO W, et al. Secure multidimensional interconnection network for the software defined system on wafer[J]. Chinese Journal of Network and Information Security, 2025, 11(2): 102-114. DOI: 10.11959/j.issn.2096-109x.2025020.
Secure multidimensional interconnection network for the software defined system on wafer
To address data integrity attacks between dielets in software defined systems on wafer (SDSoW)
a secure multidimensional network on wafer (SMNoW) architecture based on dynamic heterogeneous redundancy (DHR) was proposed. A unified circuit switching (CS) and packet switching (PS) structure was implemented
and a DHR-based multipath transmission model was developed. This model supported same dimensional
different dimensional
and mixed dimensional heterogeneous multipath transmission. An algorithm for multipath selection and computation was proposed to construct heterogeneous multipaths based on interface status. To meet varying requirements
multipath transmission methods based on first packet replication
packet-by-packet replication
and all packets replication were achieved through a packet transmission and policy arbitration mechanism. The proposed SMNoW was tested in a network on wafer system based on the unified CS and PS structure. Experimental analysis shows that the proposed architecture increases transmission success rates from 35.4% to 94.8% compared to typical multipath arbitration feedback transmission methods under multipath collaborative attacks. The performance of a 16×16 multidimensional network on wafer was evaluated using the OMNeT platform. Results indicate that by selecting appropriate transmission modes and interconnection dimensions
the proposed architecture could achieve delay characteristics comparable to traditional multipath (MP) transmission. Furthermore
under security attacks
the proposed architecture achieves up to 37.37% transmission delay optimization compared to MP.
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