High speed national secret SM4 optical fiber communication system scheme based on FPGA

Peiyu HUANG; Jiabo SONG; Yangfan JIA

doi:10.11959/j.issn.2096-109x.2023082

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High speed national secret SM4 optical fiber communication system scheme based on FPGA

Papers | 更新时间：2024-06-03

- High speed national secret SM4 optical fiber communication system scheme based on FPGA
- Chinese Journal of Network and Information Security Vol. 9, Issue 6, Pages: 46-55(2023)
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- DOI：10.11959/j.issn.2096-109x.2023082
  CLC： TN918
- Online First：2023-12，
  
  Published：25 December 2023
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Peiyu HUANG, Jiabo SONG, Yangfan JIA. High speed national secret SM4 optical fiber communication system scheme based on FPGA[J]. Chinese Journal of Network and Information Security, 2023, 9(6): 46-55.
DOI：

Peiyu HUANG, Jiabo SONG, Yangfan JIA. High speed national secret SM4 optical fiber communication system scheme based on FPGA[J]. Chinese Journal of Network and Information Security, 2023, 9(6): 46-55. DOI： 10.11959/j.issn.2096-109x.2023082.

摘要

随着光纤通信技术在工业物联网中的广泛应用，越来越多的密码算法被应用到物联网嵌入式设备中来保障数据传输的安全性。其中，SM4 分组密码算法是我国自主研发的商用密码算法，应用于无线局域网和物联网数据加密。嵌入式设备在光纤保密通信中对加解密速度要求很高，通过软件进行加解密的速度较慢，满足不了实时性高的应用场景。因此，基于现场可编程门阵列（FPGA，field programmable gate array）和SM4算法，设计了实时性高、安全性强的光纤通信系统。通过FPGA实现SM4算法加解密以及数据传输的介质访问控制（MAC，medium access control）层接口处理，提出SM4算法硬件实现架构的优化方案，采用流水线的方式缩短关键路径，提高系统时钟频率，并通过S盒变换并行处理加快数据的替换操作，结合双缓存的处理方式，减小数据读取时延，使缓存区数据处理更加容易，丢包率大大减小，所提方案极大地提高了系统数据的吞吐量。实验结果表明，所提方案的 SM4 算法加解密模块与同类型设计相比，在资源消耗相差不大的情况下吞吐量更大，可达 25.6 Gbit/s，受限于万兆 SFP+光模块，整个光纤通信系统吞吐量最高为 9.4 Gbit/s，对于128 bit数据加密平均耗时为0.47 μs，解密平均耗时为0.28 μs，可应用于多种物联网保密通信场景。

Abstract

With the increasing use of optical fiber communication technology in the Industrial Internet of Things

cryptographic algorithms play a crucial role in ensuring the security of data transmission in embedded device environments.The SM4 packet cipher algorithm

developed independently in our country

is widely applied to wireless LAN and Internet of Things data encryption.However

the software-based encryption and decryption processes are relatively slow

which hampers their application in scenarios requiring high real-time performance

especially for embedded devices.To address this issue

a high-performance and secure optical fiber communication system was designed based on the FPGA platform and the SM4 algorithm.The FPGA was used to implement the MAC layer interface for SM4 algorithm encryption and decryption

as well as data transmission.Besides

an optimization scheme for the hardware implementation architecture of the SM4 algorithm was proposed.The critical path was shortened by employing a pipeline method

thereby improving the system clock frequency.Additionally

parallel processing of S-box transformation was accelerated to enable efficient data replacement.To reduce data reading delays

a dual-cache processing method was combined to facilitate easier processing of cache data and significantly reduce packet loss rates.This scheme greatly enhanced system data throughput.Experimental results demonstrate that compared to similar designs

the throughput of the SM4 algorithm encryption and decryption module in this scheme reaches up to 25.6 Gbit/s

with minimal differences in resource consumption.Due to limitations imposed by the 10-gigabit SFP+ optical module

the throughput of the entire optical fiber communication system reaches 9.4 Gbit/s.For 128-bit data

the average encryption speed is 0.47 μs/bit and the average decryption speed is 0.28 μs/bit

which can be applied to a variety of secure communication scenarios in the internet of things.

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