Compact software/hardware co-design and implementation method of Aigis-sig digital signature scheme

Zhen ZHOU; Debiao HE; Min LUO; Li LI

doi:10.11959/j.issn.2096-109x.2021026

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Compact software/hardware co-design and implementation method of Aigis-sig digital signature scheme

Topic: Integrated Circuit Hardware Security | 更新时间：2024-06-03

- Compact software/hardware co-design and implementation method of Aigis-sig digital signature scheme
- Chinese Journal of Network and Information Security Vol. 7, Issue 2, Pages: 64-76(2021)
- 作者机构：
  
  1. 空天信息安全与可信计算教育部重点实验室，湖北武汉 430072
  2. 武汉大学国家网络安全学院，湖北武汉 430072
- 作者简介：
- 基金信息：
- DOI：10.11959/j.issn.2096-109x.2021026
  CLC： TN918
- Online First：2021-04，
  
  Published：15 April 2021
- 稿件说明：
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Zhen ZHOU, Debiao HE, Min LUO, et al. Compact software/hardware co-design and implementation method of Aigis-sig digital signature scheme[J]. Chinese Journal of Network and Information Security, 2021, 7(2): 64-76.
DOI：

Zhen ZHOU, Debiao HE, Min LUO, et al. Compact software/hardware co-design and implementation method of Aigis-sig digital signature scheme[J]. Chinese Journal of Network and Information Security, 2021, 7(2): 64-76. DOI： 10.11959/j.issn.2096-109x.2021026.

摘要

基于理想格构造的 Aigis-sig 数字签名方案具有实现效率高、签名长度短、抗量子攻击等优势。针对Aigis-sig方案，构造了一种改进的模乘计算元件，设计了一种基于快速数论变换（NTT）算法实现环上多项式运算的紧凑硬件架构；同时以此架构为基础，提出了Aigis-sig数字签名方案的FPGA软硬件协同实现方法。实验表明，在Xilinx Zynq-7000 SoC平台上，CPU频率和硬件频率分别设置为666.66 MHz和150 MHz时，该实现方案相较于纯软件实现，签名阶段和验签阶段分别取得约26%和17%的性能提升。

Abstract

Digital signature scheme Aigis-sig

constructed on ideal lattice

takes the advantages of high efficiency

short signature length and resistant to quantum attack

etc.An optimized modular multiplication arithmetic component was constructed and a compact hardware architecture for polynomial operation over a ring based on number theory transformation (NTT) algorithm for Aigis-sig was designed.Besides

based on this architecture

software/hardware co-design and implementation for Aigis-sig scheme on FPGA platform in cryptography was proposed.Experimental results show that the speed of signature phase and verification phase are increased by about 26% and 17% respectively

compared with the pure software implementation on Xilinx Zynq-7000 SoC platform when CPU clock frequency and hardware clock frequency are set as 666.66MHz and 150 MHz respectively.

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references

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