Based on linear systolic array for convolutional neural network’s calculation optimization and performance analysis

Qinrang LIU; Chongyang LIU; Jun ZHOU; Xiaolong WANG

doi:10.11959/j.issn.2096-109x.2018100

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Based on linear systolic array for convolutional neural network’s calculation optimization and performance analysis

Papers | 更新时间：2024-06-03

- Based on linear systolic array for convolutional neural network’s calculation optimization and performance analysis
- Chinese Journal of Network and Information Security Vol. 4, Issue 12, Pages: 16-24(2018)
- 作者机构：
- 作者简介：
- 基金信息：
- DOI：10.11959/j.issn.2096-109x.2018100
  CLC： TP183
- Online First：2018-12，
  
  Published：15 December 2018
- 稿件说明：
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Qinrang LIU, Chongyang LIU, Jun ZHOU, et al. Based on linear systolic array for convolutional neural network’s calculation optimization and performance analysis[J]. Chinese Journal of Network and Information Security, 2018, 4(12): 16-24.
DOI：

Qinrang LIU, Chongyang LIU, Jun ZHOU, et al. Based on linear systolic array for convolutional neural network’s calculation optimization and performance analysis[J]. Chinese Journal of Network and Information Security, 2018, 4(12): 16-24. DOI： 10.11959/j.issn.2096-109x.2018100.

摘要

针对大部分FPGA端上的卷积神经网络（CNN

convolutional neural network）加速器设计未能有效利用稀疏性的问题，从带宽和能量消耗方面考虑，提出了基于线性脉动阵列的2种改进的CNN计算优化方案。首先，卷积转化为矩阵相乘形式以利用稀疏性；其次，为解决传统的并行矩阵乘法器存在较大I/O需求的问题，采用线性脉动阵列改进设计；最后，对比分析了传统的并行矩阵乘法器和2种改进的线性脉动阵列用于CNN加速的利弊。理论证明及分析表明，与并行矩阵乘法器相比，2种改进的线性脉动阵列都充分利用了稀疏性，具有能量消耗少、I/O带宽占用少的优势。

Abstract

Concerning the issue that the convolutional neural network (CNN) accelerator design on most FPGA ends fails to effectively use the sparsity and considering both bandwidth and energy consumption

two improved CNN calculation optimization strategies based on linear systolic array architecture are proposed.Firstly

convolution is transformed into matrix multiplication to take advantage of sparsity.Secondly

in order to solve the problem of large I/O demand in traditional parallel matrix multiplier

linear systolic array is used to improve the design.Finally

a CNN acceleration comparative analysis of the advantages and disadvantages between parallel matrix multiplier and two improved linear systolic arrays is presented.Theoretical proof and analysis show that compared with the parallel matrix multiplier

the two improved linear systolic arrays make full use of sparsity

and have the advantages of less energy consumption and less I/O bandwidth occupation.

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references

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